Reducing branch misprediction penalty through multipath execution
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Control-flow misprediction penalties are a major impediment to high performance in wide-issue superscalar processors. If the current trend continues, with issue widths getting larger and misprediction latencies getting longer due to deeper pipelines, efficient control-flow handling will continue to be one of the central challenges in microarchitecture design.
This work proposes and evaluates an alternative form of misprediction penalty reduction through multipath execution. The proposed form of multipath execution, Selective Eager Execution, recognizes the fact that some branches are more predictable than others. For less predictable branches, selective eager execution offers reduced misprediction penalties by trading off reduced latency with increased processing bandwidth requirements.
One contribution of this work is the introduction of branch confidence estimation into the domain of multipath execution, and the evaluation of several confidence estimators for their fitness in this domain. The work establishes the fact that selective eager execution can be used to decrease effective misprediction penalties and that it complements performance improvements in branch prediction accuracy. Another contribution of this research is to show that it is feasible to integrate multipath capabilities into current high-performance processor microarchitectures with a small amount of additional hardware. The work proposes the POLYPATH processor architecture, which is described and evaluated in detail on a number of different hardware configurations and benchmark applications.