Stress analysis of shallow trench isolation for 256 M DRAM and beyond

The stress generation of the shallow trench isolation has been systematically investigated using the stress simulation and the experiment. It is found that the scale-down of the isolation pitch causes a remarkable stress generation due to the overlap of the stress from both trench sides. Therefore a small isolation pitch causes the crystal defects generation with ease. We carried out the stress analysis against the various process parameters in detail. The high temperature sacrificial oxidation can effectively eliminate the stress generation. It was confirmed that enough isolation characteristics can maintain up to 0.1 /spl mu/m regime to give a careful consideration of the stress reduction.

[1]  P. Fazan,et al.  A highly manufacturable trench isolation process for deep submicron DRAMs , 1993, Proceedings of IEEE International Electron Devices Meeting.

[2]  Satoru Kawazu,et al.  Stable Solution Method for Viscoelastic Oxidation Including Stress-Dependent Viscosity , 1996 .

[3]  Andres Bryant,et al.  Characteristics of CMOS device isolation for the ULSI age , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[4]  S.H. Hong,et al.  Stress minimization in deep sub-micron full CMOS devices by using an optimized combination of the trench filling CVD oxides , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[5]  John Damiano,et al.  Characterization and elimination of trench dislocations , 1998, 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).