Wafer level packaging (WLP): Fan-in, fan-out and three-dimensional integration

In this paper, the state-of-the-art results of research and development in wafer-level packaging (WLP) is reviewed. The paper starts from the introduction of several fan-in wafer-level packaging technologies. The focus is given on the fan-in WLP reliability performance as related to the structural differences. New failure mechanisms that appear in build-up stack layers are discussed. Next, emerging fan-out wafer level packaging technologies are introduced. Several key challenges in fan-out WLP technologies are examined. Finally, Three-dimensional (3-D) integration of through-silicon-via (TSV) technology and wafer-level bonding technology with WLP, especially in MEMS and image sensor applications, is discussed.

[1]  Deok-Hoon Kim,et al.  Wafer level packaging having bump-on-polymer structure , 2003, Microelectron. Reliab..

[2]  W.D. van Driel,et al.  Interfacial Delamination Mechanisms During Soldering Reflow With Moisture Preconditioning , 2008, IEEE Transactions on Components and Packaging Technologies.

[3]  Peter Elenius,et al.  Solder joint reliability of a polymer reinforced wafer level package , 2002, 52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345).

[4]  Q. Han,et al.  Experimental investigations and model study of moisture behaviors in polymeric materials , 2009, Microelectron. Reliab..

[5]  Xuejun Fan,et al.  Effects of design, structure and material on thermal-mechanical reliability of large array wafer level packages , 2009, 2009 International Conference on Electronic Packaging Technology & High Density Packaging.

[6]  B. Keser,et al.  Advanced Packaging: The Redistributed Chip Package , 2007, IEEE Transactions on Advanced Packaging.

[7]  Q. Han,et al.  Design and optimization of thermo-mechanical reliability in wafer level packaging , 2010, Microelectron. Reliab..

[8]  Xuejun Fan,et al.  Design and Reliability in Wafer Level Packaging , 2008, 2008 10th Electronics Packaging Technology Conference.

[9]  M. Takahashi,et al.  Wafer Process Chip Size Package Consisting of Double-Bump Structure for Small-Pin-Count Packages , 2005, Proceedings Electronic Components and Technology, 2005. ECTC '05..

[10]  Tiao Zhou,et al.  Board level temperature cycling study of large array Wafer Level Package , 2009, 2009 59th Electronic Components and Technology Conference.

[11]  R. Anderson,et al.  Advanced Analysis of WLCSP Copper Interconnect Reliability under Board Level Drop Test , 2008, 2008 10th Electronics Packaging Technology Conference.

[12]  Xuejun Fan,et al.  A Micromechanics-Based Vapor Pressure Model in Electronic Packages , 2005 .

[13]  Cheng-Ta Ko,et al.  Wafer-level bonding/stacking technology for 3D integration , 2010, Microelectron. Reliab..

[14]  Ahmer Syed,et al.  Design for board trace reliability of WLCSP under drop test , 2009, EuroSimE 2009 - 10th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems.

[15]  Tong Yan,et al.  INTEGRATED TESTING, MODELING AND FAILURE ANALYSIS OF CSP Nl FOR ENHANCED BOARD LEVEL RELIABILITY , 2010 .

[16]  M. Brunnbauer,et al.  Embedded Wafer Level Ball Grid Array (eWLB) , 2008, 2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT).

[17]  G. Q. Zhang,et al.  Multi-physics modeling in virtual prototyping of electronic packages--combined thermal, thermo-mechanical and vapor pressure modeling , 2004, Microelectron. Reliab..

[18]  J. Fan,et al.  Direct Concentration Approach of Moisture Diffusion and Whole-Field Vapor Pressure Modeling for Reflow Process — Part II : Application to 3 D Ultrathin Stacked-Die Chip Scale Packages , 2009 .

[19]  Xunqing Shi,et al.  Direct Concentration Approach of Moisture Diffusion and Whole-Field Vapor Pressure Modeling for Reflow Process—Part I: Theory and Numerical Implementation , 2009 .

[20]  Michael Johnson,et al.  Solder joint reliability of a polymer reinforced wafer level package , 2002, Microelectron. Reliab..

[21]  Xunqing Shi,et al.  Direct Concentration Approach of Moisture Diffusion and Whole-Field Vapor Pressure Modeling for Reflow Process—Part II: Application to 3D Ultrathin Stacked-Die Chip Scale Packages , 2009 .

[22]  Xuejun Fan,et al.  Shock performance study of solder joints in wafer level packages , 2009, 2009 International Conference on Electronic Packaging Technology & High Density Packaging.