A new parallel hardware architecture for high-performance stereo matching calculation

In this paper, we propose a hardware (H/W) architecture to find disparities for stereo matching in real time. After analyzing the arithmetic characteristic of stereo matching, we propose a new calculating method that reuses the intermediate results to minimize the calculation load and memory access. From this, we propose a stereo matching calculation cell and a new H/W architecture. Finally, we propose a new stereo matching processor. The implemented H/W can operate at the clock frequency of 250MHz at least in the FPGA (field programmable gate array) environment and produce about 120 disparity images per second for HD stereo images. A H/W architecture for real-time stereo matching.Analysis of the arithmetic characteristic of stereo matching.Method to reuse the intermediate results.Method to minimize the calculation load and memory access.Expandable hardware for 1D and 2D operation.

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