论文信息 - VISA: A variable instruction set architecture

VISA: A variable instruction set architecture

This paper presents an instruction coding technique that allows to reduce the instruction width without limiting the exploitation of the machine resources. This result can be obtained by a dynamic instruction coding managed by the compiler.The technique has been applied to a VLIW-structured machine. The machine has an instruction width of 32 bits, while the number of bits needed to code all the functions the machine can perform in a cycle is 98.

Alessandro De Gloria

[1] Emmanuel Katevenis,et al. Reduced instruction set computer architectures for VLSI , 1984 .

[2] Robert P. Colwell,et al. A VLIW architecture for a trace scheduling compiler , 1987, ASPLOS.

[3] John R. Ellis,et al. Bulldog: a compiler for vliw architectures (parallel computing, reduced-instruction-set, trace scheduling, scientific) , 1985 .

[4] JOHN L. HENNESSY,et al. VLSI Processor Architecture , 1984, IEEE Transactions on Computers.

[5] Carlo H. Séquin,et al. A VLSI RISC , 1982, Computer.

[6] Robert P. Colwell,et al. A VLIW architecture for a trace scheduling compiler , 1987, ASPLOS 1987.

[7] Fred C. Chow,et al. How many addressing modes are enough? , 1987, ASPLOS.

[8] Joseph A. Fisher,et al. Trace Scheduling: A Technique for Global Microcode Compaction , 1981, IEEE Transactions on Computers.

[9] John R. Ellis,et al. Bulldog: A Compiler for VLIW Architectures , 1986 .