PETS: Power and energy estimation tool at system-level

In this paper, we introduce PETS, a simulation based tool to estimate, analyse and optimize power/energy consumption of an application running on complex state-of-the-art heterogeneous embedded processor based platforms. This tool is integrated with power and energy models in order to support comprehensive design space exploration for low power multi-core and heterogeneous multiprocessor platforms such as OMAP, CARMA, Zynq 7000 and Virtex II Pro. Moreover, PETS is equipped with power optimization techniques such as dynamic slack reduction and work load balancing. The development of PETS involves two steps. First step: power model generation. For the power model development, functional-level parameters are used to set up generic power models for the different components of the system. So far, seven power models have been developed for different architectures, starting from the simple low power architecture ARM9 to the very complex DSP TI C64x. Second step: a simulation based virtual platform framework is developed using SystemC IP's and JIT/ISS compilers to accurately grab the activities to estimate power. The accuracy of our proposed tool is evaluated by using a variety of industrial benchmarks. Estimated power and energy values are compared to real board measurements. The power estimation results are less than 4% of error for single core processor, 4.6% for dual-core processor, 5% for quad-core, 6.8% multi-processor based system and effective optimisation of power/energy for the applications.

[1]  David R. Kaeli,et al.  Multi2Sim: A simulation framework for CPU-GPU computing , 2012, 2012 21st International Conference on Parallel Architectures and Compilation Techniques (PACT).

[2]  Luca Fossati,et al.  ReSP: A Nonintrusive Transaction-Level Reflective MPSoC Simulation Platform for Design Space Exploration , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Andy D. Pimentel,et al.  A Signature-Based Power Model for MPSoC on FPGA , 2012, VLSI Design.

[4]  Alain Greiner,et al.  Parallel simulation of systemC TLM 2.0 compliant MPSoC on SMP workstations , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[5]  Stijn Eyerman,et al.  Fine-grained DVFS using on-chip regulators , 2011, TACO.

[6]  Jean-Luc Dekeyser,et al.  Hybrid system level power consumption estimation for FPGA-based MPSoC , 2011, 2011 IEEE 29th International Conference on Computer Design (ICCD).

[7]  Cécile Belleudy,et al.  Hybrid power management in real time embedded systems: an interplay of DVFS and DPM techniques , 2011, Real-Time Systems.

[8]  Jean-Luc Dekeyser,et al.  An efficient power estimation methodology for complex RISC processor-based platforms , 2012, GLSVLSI '12.

[9]  Geert Vanmeerbeeck,et al.  Automatic workload generation for system-level exploration based on modified GCC compiler , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[10]  Osman S. Unsal,et al.  System-level power estimation tool for embedded processor based platforms , 2014, RAPIDO '14.

[11]  Jung Ho Ahn,et al.  McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[12]  Margaret Martonosi,et al.  Wattch: a framework for architectural-level power analysis and optimizations , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[13]  Eric Senn,et al.  Functional level power analysis: an efficient approach for modeling the power consumption of complex processors , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[14]  Zhiyuan Li,et al.  Energy-Aware Scheduling for Real-Time Multiprocessor Systems with Uncertain Task Execution Time , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[15]  V. Sruk,et al.  Mapping algorithms for MPSoC synthesis , 2010, The 33rd International Convention MIPRO.

[16]  Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013 , 2013, DATE.

[17]  Kenji Funaoka,et al.  Dynamic voltage and frequency scaling for optimal real-time scheduling on multiprocessors , 2008, 2008 International Symposium on Industrial Embedded Systems.

[18]  Mahmut T. Kandemir,et al.  The design and use of simplePower: a cycle-accurate energy estimation tool , 2000, Proceedings 37th Design Automation Conference.

[19]  Luciano Lavagno,et al.  Efficient power co-estimation techniques for system-on-chip design , 2000, DATE '00.