Latency Insertion Method (LIM) for Electro-Thermal Analysis of 3-D Integrated Systems at Pre-Layout Design Stages

In this paper, a fast circuit simulation technique based on the latency insertion method (LIM) is proposed for the electro-thermal analysis of circuits and high-performance systems. Application of the method to the problems specific to the early pre-layout design stages is considered. This method can be particularly useful for the early tradeoff and feasibility studies of on-chip and off-chip interconnect systems as well as of entire chip and package structures. The proposed method is shown to be suitable for modeling of both electrical and thermal phenomena occurring in high-speed high-performance very large scale integration circuits at the pre-layout design stages. Capability of the LIM to perform steady state and transient thermal analysis of a 3-D integrated circuit model is demonstrated with an example derived from an actual industry design. The experiments carried out in this paper demonstrate that the proposed methodology significantly outperforms conventional computer-aided design tools.

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