The application of hierarchical trees to circuit partitioning, clock net routing, and connectivity verification problems

The increase of microelectronic system complexity has imposed new challenges for physical design problems. In this dissertation, we investigate three problems at various stages in physical design by applying a hierarchical tree abstraction. Circuit partitioning plays a fundamental role in Design Automation for problem decomposition. The partitioning of a system can be viewed as assigning operations on a hierarchical tree from board levels down to macro-cell levels. As the circuit complexity increases, outputs generated by the commonly adopted recursive partitioning algorithms are degenerating due to their tendency of acquiring good quality for higher levels at the expense of that for lower levels. Hence we propose a partitioning paradigm using the Set Covering formulation to replace recursive partitioning. By combining a micro-global, macro-global Local Ratio Cut clustering scheme, our approach reduces the number of required devices by 29% and the run time by 78% for a large benchmark (160K gates). After the partitioning and the placement phases, positions of synchronizing elements are determined. The next task is to route the clock net. The clock net routing is commonly represented by a Steiner tree with the clock source as the root and clock sinks as leaves. We propose a general, simulated annealing based zero-skew clock net construction algorithm which works in any routing space, with the added flexibility of optimizing either the wire length or the propagation delay. Experimental results have shown that our algorithm can achieve substantial delay reduction and encouraging wire length minimization compared to previous works using the same benchmarks. The Multichip Module (MCM) is a popular packaging alternative for complicated, performance-driven designs. Before die mounting, validating the substrate integrity is crucial for product performance and reliability. Consequently, we propose a test generation/optimization algorithm for MCM substrate verification using two-probe testers, which reduces the testing time while providing complete fault coverage. This objective is achieved by formulating the designs as routing trees which allows us to eliminate the redundancies and to perform efficient probe schedulings. Our algorithm reduces the testing time by over 38% when compared to a patented package based on industrial substrates with complete fault coverage.