New visions for IC yield detractor detection

The observability of conventional electrical test site and imaging techniques needs to be extended and coupled with all of the actual product layout attributes in order to reflect the relevant yield detractors of the current technologies in production and development. This paper discusses new electrical test site strategies that have been recently developed and deployed developed for parametric yield detection and systematic hard defect detection by layout attribute. Such test structures are derived from the actual product and in some key cases also embedded in the product utilizing available space between the active circuitry and detected in-line with non-contact techniques.