New CMOS four-quadrant multiplier and squarer circuits
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Cheng-Chieh Chang | Shen-Iuan Liu | Yuh-Shyan Hwang | Shen-Iuan Liu | Cheng-Chieh Chang | Yuh-Shyan Hwang
[1] K. Kimura. A Dynamic Bias Current Technique for a Bipolar Exponential-Law Element and a CMOS Square-Law Element Usable with Low Supply Voltage (Special Section of Letters Selected from the 1994 IEICE Spring Conference) , 1994 .
[2] Shen-Iuan Liu,et al. CMOS four-quadrant multiplier using bias offset crosscoupled pairs , 1993 .
[3] Mohammed Ismail,et al. High frequency wide range CMOS analogue multiplier , 1992 .
[4] Mohammed Ismail,et al. A CMOS square-law programmable floating resistor independent of the threshold voltage , 1992 .
[5] Ho-Jun Song,et al. An MOS four-quadrant analog multiplier using simple two-input squaring circuits with source followers , 1990 .
[6] Randall L. Geiger,et al. VLSI Design Techniques for Analog and Digital Circuits , 1989 .
[7] J.S. Pena-Finol,et al. A MOS four-quadrant analog multiplier using the quarter-square technique , 1987 .
[8] S. B. Park,et al. Four-quadrant CMOS analogue multiplier , 1987 .
[9] E. Seevinck,et al. A versatile CMOS linear transconductor/square-law function , 1987 .
[10] J. Pena-Finol,et al. A four quadrant MOS analog multiplier , 1987, 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[11] K. Bult,et al. A CMOS Four-Quadrant Analog Multiplier , 1986 .
[12] J.N. Babanezhad,et al. A 20-V four-quadrant CMOS analog multiplier , 1985, IEEE Journal of Solid-State Circuits.
[13] D.C. Soo,et al. A four-quadrant NMOS analog multiplier , 1982, IEEE Journal of Solid-State Circuits.