The simulation technique for large-scale tree structured interconnects

An accurate and efficient method for modeling and analysis of on-chip interconnects is presented in this paper. The proposed technique is based on circuit decomposition approach and provides the recursive calculation of 7-tree transfer function. The symbolic expressions of voltage transfer functions of the large-scale integrated interconnect structures are determined. To demonstrate the validity of the proposed method, lumped 7-tree networks of different levels for the microelectronic interconnect application are simulated. Excellent agreement between the modeling results and SPICE-computations is found both in frequency- and time-domains.

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