On SPARC LEON-2 ISA Extensions Experiments for MPEG Encoding Acceleration

This paper presents the necessary steps to modify the implementation of the SPARCV8 architecture to enhance it with multimedia-oriented instructions. The purpose is improving video compression performance without designing dedicated coprocessors. We investigate the complexity of modifying a standard processor instruction set and show that, although not trivial, this is feasible in a few weeks. We implemented 12 new instructions and use some of them to optimize the computation of a demanding step of the MPEG encoding. The result is a performance increase of 67% in the execution of a part of this algorithm, allowing us to expect a 30% speedup in the execution of an MPEG video compression. The area increase of the integer unit is about 18% and the clock frequency is not significantly modified in an LEON-2 implementing 6 among 12 of the new instructions.

[1]  Norman P. Jouppi,et al.  Performance of image and video processing with general-purpose processors and media ISA extensions , 1999, ISCA.

[2]  Mickey Gutman,et al.  Complete Guide to Mmx Technology , 1997 .

[3]  Jiri Gaisler.  A portable and fault-tolerant microprocessor based on the SPARC v8 architecture , 2002, Proceedings International Conference on Dependable Systems and Networks.

[4]  Marc Tremblay,et al.  VIS speeds new media processing , 1996, IEEE Micro.

[5]  Johann Großschädl,et al.  A Simple Architectural Enhancement for Fast and Flexible Elliptic Curve Cryptography over Binary Finite Fields GF(2m) , 2004, Asia-Pacific Computer Systems Architecture Conference.

[6]  Geoffrey Brown,et al.  Lx: a technology platform for customizable VLIW embedded processing , 2000, ISCA '00.

[7]  AdveSarita,et al.  Performance of image and video processing with general-purpose processors and media ISA extensions , 1999 .

[8]  Antonio Núñez,et al.  Flexible design of SPARC cores: a quantitative study , 1999, Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES'99) (IEEE Cat. No.99TH8450).

[9]  Jürgen Becker,et al.  Scalable processor instruction set extension , 2005, IEEE Design & Test of Computers.

[10]  B. Ramakrishna Rau,et al.  Automatic architectural synthesis of VLIW and EPIC processors , 1999, Proceedings 12th International Symposium on System Synthesis.

[11]  Ingrid Verbauwhede,et al.  A realtime, memory efficient fingerprint verification system , 2004, 2004 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[12]  Saman P. Amarasinghe,et al.  Exploiting superword level parallelism with multimedia instruction sets , 2000, PLDI '00.

[13]  Albert Wang,et al.  Hardware/software instruction set configurability for system-on-chip processors , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[14]  Jack Sklansky,et al.  Conditional-Sum Addition Logic , 1960, IRE Trans. Electron. Comput..