Complexity Bounds for Lookup Table Implementation of Factored Forms in FPGA Technology Mapping

We consider tec hnology mapping from factored form (binary leaf-D A G)to lookup tables (LUTs), such as those found in field programmable gate arrays. Polynomial time algorithms exist for (in the worst case) optimal mapping of a single-output function. The worst case occurs when the leaf-DA G is a tree. Previous results gave a tight upper bound on the number of LUTs required for LUTs with up to 5 inputs (and a bound with 6 inputs). The bounds are a function of the number of literals and the LUT size. We extend these results to tight bounds for LUTs with an arbitrary number of inputs.

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