An optimal warning-zone-length assignment algorithm for real-time and multiple-QoS on-chip bus arbitration

In an advanced System-on-Chip (SoC) for real-time applications, the arbiter of its on-chip communication subsystem needs to support multiple QoS criteria while providing a hard real-time guarantee. To fulfill both objectives, the arbitration algorithm must dynamically switch between NonReal-Time (NRT) and Real-Time (RT) modes such that use of the RT mode is minimized to best accommodate the overall QoS criteria. In this article, we define a model for this problem, and propose optimal solutions to its associated problems with static and dynamic warning-zone-length assignment. Compared with previous works, the proposed approach enables a bus arbiter to use much less RT mode in providing a Real-Time (RT) guarantee and, therefore, gives the arbiter more opportunity to employ non-RT modes to achieve better overall QoS. Experimental results show that the proposed approach reduces RT mode usage by as much as 37.1%. Moreover, that reduction in RT mode usage helps cut the execution time by 27.0% when applying our approach to an industrial DRAM controller. Another case study on an AMBA-compliant ultra-high-resolution H.264 decoder IP shows that the proposed approach reduces RT mode usage by 26.4%, which leads to an average reduction of 10.4% in decoding time. Finally, when implementing a 16 master arbiter, it costs only 6.9K and 9.5K gates of overhead using the proposed static and dynamic approach, respectively. Therefore, the proposed approach is suitable for real-time SoC applications.

[1]  Rodney R. Howell,et al.  On Non-Preemptive Scheduling of Recurring Tasks Using Inserted Idle Times , 1995, Inf. Comput..

[2]  Sang Hyuk Son,et al.  A feedback control approach for guaranteeing relative delays in Web servers , 2001, Proceedings Seventh IEEE Real-Time Technology and Applications Symposium.

[3]  Paul Muhlethaler,et al.  A Few Results on Non-Preemptive Real Time Scheduling , 1999 .

[4]  Jian-Wen Chen,et al.  A Highly Integrated 8mW H.264/AVC Main Profile Real-time CIF Video Decoder on a 16MHz SoC Platform , 2007, 2007 Asia and South Pacific Design Automation Conference.

[5]  Naehyuck Chang,et al.  Slack-based Bus Arbitration Scheme for Soft Real-time Constrained Embedded Systems , 2007, 2007 Asia and South Pacific Design Automation Conference.

[6]  Lui Sha,et al.  Mode change protocols for priority-driven preemptive scheduling , 1989, Real-Time Systems.

[7]  Charles U. Martel,et al.  On non-preemptive scheduling of period and sporadic tasks , 1991, [1991] Proceedings Twelfth Real-Time Systems Symposium.

[8]  Chita R. Das,et al.  A hybrid SoC interconnect with dynamic TDMA-based transaction-less buses and on-chip networks , 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

[9]  Joseph Sifakis,et al.  Fine grain QoS control for multimedia application software , 2005, Design, Automation and Test in Europe.

[10]  Jing-Yang Jou,et al.  A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication , 2006, Asia and South Pacific Conference on Design Automation, 2006..

[11]  Chein-Wei Jen,et al.  An efficient quality-aware memory controller for multimedia platform SoC , 2005, IEEE Transactions on Circuits and Systems for Video Technology.

[12]  Radu Marculescu,et al.  Prediction-based flow control for network-on-chip traffic , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[13]  Luca Benini,et al.  Performance Analysis of Arbitration Policies for SoC Communication Architectures , 2003, Des. Autom. Embed. Syst..

[14]  Krishnendu Chakrabarty,et al.  Pruning-based, energy-optimal, deterministic I/O device scheduling for hard real-time systems , 2005, TECS.

[15]  Douglas C. Schmidt,et al.  The Design and Performance of a Real-Time CORBA Scheduling Service , 2001, Real-Time Systems.

[16]  Sujit Dey,et al.  Evaluation of the traffic-performance characteristics of system-on-chip communication architectures , 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.

[17]  Gene F. Franklin,et al.  Digital control of dynamic systems , 1980 .

[18]  Richard S. Sutton,et al.  Reinforcement Learning: An Introduction , 1998, IEEE Trans. Neural Networks.

[19]  Cheng-Kok Koh,et al.  Improving the scalability of SAMBA bus architecture , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[20]  Axel Jantsch,et al.  Interconnect-Centric Design for Advanced SOC and NOC , 2010 .

[21]  Alan Burns,et al.  Real Time Scheduling Theory: A Historical Perspective , 2004, Real-Time Systems.

[22]  James W. Layland,et al.  Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment , 1989, JACM.

[23]  B. Anderson,et al.  Digital control of dynamic systems , 1981, IEEE Transactions on Acoustics, Speech, and Signal Processing.

[24]  Alberto L. Sangiovanni-Vincentelli,et al.  A tool for describing and evaluating hierarchical real-time bus scheduling policies , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[25]  Ran Ginosar,et al.  QNoC: QoS architecture and design process for network on chip , 2004, J. Syst. Archit..

[26]  Performance analysis of different arbitration algorithms of the AMBA AHB bus , 2004, Proceedings. 41st Design Automation Conference, 2004..

[27]  Kees G. W. Goossens,et al.  Cost-performance trade-offs in networks on chip: a simulation-based approach , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[28]  Martin L. Puterman,et al.  Markov Decision Processes: Discrete Stochastic Dynamic Programming , 1994 .

[29]  Joonwon Lee,et al.  Runtime feasibility check for non-preemptive real-time periodic tasks , 2006, Inf. Process. Lett..

[30]  Kees G. W. Goossens,et al.  A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification , 2005, Design, Automation and Test in Europe.

[31]  Alberto L. Sangiovanni-Vincentelli,et al.  Period Optimization for Hard Real-time Distributed Automotive Systems , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[32]  Richard S. Sutton,et al.  Introduction to Reinforcement Learning , 1998 .

[33]  Ganesh Lakshminarayana,et al.  The LOTTERYBUS on-chip communication architecture , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[34]  Jing-Yang Jou,et al.  A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC Buses , 2007, 2007 Asia and South Pacific Design Automation Conference.

[35]  Reinder J. Bril,et al.  QoS Control Strategies for High-Quality Video Processing , 2004, Proceedings. 16th Euromicro Conference on Real-Time Systems, 2004. ECRTS 2004..

[36]  Chung Laung Liu,et al.  Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment , 1989, JACM.

[37]  BeniniLuca,et al.  Performance Analysis of Arbitration Policies for SoC Communication Architectures , 2003 .

[38]  Tetsuro Takizawa,et al.  An efficient memory arbitration algorithm for a single chip MPEG2 AV decoder , 2001, IEEE Trans. Consumer Electron..

[39]  Paul Muhlethaler,et al.  Optimality and non-preemptive real-time scheduling revisited , 1995 .

[40]  Itu-T and Iso Iec Jtc.  Advanced video coding for generic audiovisual services , 2010 .