Automatic run-time manager generation for reconfigurable MPSoC architectures

During the last few years, new technologies have made possible to fit a larger number of components on a single die, allowing to realize more complex and heterogeneous systems, generally called Multiprocessor Systems-on-Chip (MPSoC). Additionally, the introduction of partial reconfiguration in these systems has increased both their flexibility and performance. This feature allows the designer to switch the context of a specific circuit region without any interruption in the other components, but it has also increased the level of expertise needed for their design. In this paper we introduce a Run Time Manager (RTM) able to map multiple applications on the underlying architecture and execute them concurrently. In order to ensure the RTM portability on different designs, it has been structured so that it is independent from the architecture description. It is illustrated how (1) this RTM can be automatically generated starting from the source code of the input applications, (2) its modular implementation combined with the use of partial reconfiguration allows the user to explore different policies. Finally several tests have been performed to analyse the overhead introduced by such implementation and to demonstrate that the proposed RTM can be effectively used in real case studies.