A metamodel and semantics for transaction level modeling

In this paper we present an abstract metamodel with formally defined semantics for transaction level modeling (TLM). Our objective is to capture the essence of TLM and different modeling styles in a manner which is as independent of the implementation language and simulation mechanism as possible. Such a metamodel can be used as a guideline for design of modeling libraries, modeling languages, and study of different simulation schemes. The proposed metamodel is the basis of our ongoing work in construction of TLM-specific modeling libraries and high-performance simulation kernels. As an example, we capture the the simulation semantics of two modeling styles proposed by the OSCI TLM standard.

[1]  Carlos Delgado Kloos,et al.  Reasoning about VHD3L and VHDL-AMS using denotational semantics , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

[2]  Alain Greiner,et al.  Parallel simulation of systemC TLM 2.0 compliant MPSoC on SMP workstations , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[3]  Jifeng He,et al.  Denotational Approach to an Event-Driven System-Level Language , 2008, UTP.

[4]  Matthieu Moy,et al.  jTLM: An experimentation framework for the simulation of transaction-level models of Systems-on-Chip , 2011, 2011 Design, Automation & Test in Europe.

[5]  H. Sasaki.  A formal semantics for Verilog-VHDL simulation interoperability by abstract state machine , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

[6]  Christian Haubelt,et al.  Formalizing TLM with Communicating State Machines , 2006, FDL.

[7]  Wolfgang Müller,et al.  The Formal Simulation Semantics of SystemVerilog , 2004, FDL.

[8]  Daniel Kroening,et al.  Formal verification of SystemC by automatic hardware/software partitioning , 2005, Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2005. MEMOCODE '05..

[9]  Egon Börger,et al.  Abstract State Machines. A Method for High-Level System Design and Analysis , 2003 .

[10]  Andreas Gerstlauer,et al.  The formal execution semantics of SpecC , 2002, 15th International Symposium on System Synthesis, 2002..

[11]  Wolfgang Rosenstiel,et al.  The simulation semantics of SystemC , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[12]  Daniel D. Gajski,et al.  The SpecC Language Reference Manual , 1998 .

[13]  Martin Radetzki,et al.  Modeling constructs and kernel for parallel simulation of accuracy adaptive TLMs , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[14]  Carlos Delgado Kloos,et al.  A simple denotational semantics, proof theory and a validation condition generator for unit-delay VHDL , 1995, Formal Methods Syst. Des..

[15]  Egon Brger,et al.  Formal de nition of an abstract VHDL''''93 simulator by EA - machines , 1995 .

[16]  Sandeep K. Shukla,et al.  Tackling an Abstraction Gap: Co-simulating SystemC DE with Bluespec ESL , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[17]  Alberto L. Sangiovanni-Vincentelli,et al.  Source-Level Timing Annotation and Simulation for a Heterogeneous Multiprocessor , 2008, 2008 Design, Automation and Test in Europe.