Mask manufacturability improvement by MRC
暂无分享,去创建一个
Mask data which can not be properly resolved by the mask writing tools, such as sub(resolution (reticle-scale) features or singularities can interfere with design intent or manufacturing capabilities in the absence of design guidelines or formal verification procedures. As a consequence, mask writing tools may introduce defects to device or metrology structures by snapping geometries to grid or misrepresenting process based sizing. To reduce the visibility of these defects by detuning inspection tools to release the mask with non-resolvable data in the production cycle or by waiving minimum CD rules compromises high fidelity of die pattern transfer to wafer. Driven by poor data quality, mask tool would provide degraded resolution without contextual analysis, such as correlations to the overlying and underlying mask layers and without regard to device models. The key reasons for this situation are arbitrary layout of technology structures and design layout-to-mask post-processing for OPC and fill pattern for which design has no intention or knowledge to intervene. The post-processing of mask data to eliminate errors effectively detaches design responsibility from the mask shop actions and may have other detrimental effects on the production cycle such as iterative defect analysis and long write times due to the large polygon count. In this work we propose mask rule check based on the principles to which the masks are being written and inspected. Running this mandatory rule set should reduce the product cycletime, benefit the cost and improve mask quality and reproduction of design intent. It feeds the prospective mask information back to the layout time making it possible to make design adjustments in the interest of pattern fidelity and device parameters.
[1] Artur Balasinski. Question: DRC or DfM? Answer: FMEA and ROI , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).
[2] Linard Karklin,et al. Subwavelength lithography: an impact of photomask errors on circuit performance , 2002, SPIE Advanced Lithography.