Optimized Mapping Spiking Neural Networks onto Network-on-Chip

Mapping spiking neural networks (SNNs) onto network-on-chips (NoCs) is pivotal to fully utilize the hardware resources of dedicated multi-core processors (CMPs) for SNNs’ simulation. This paper presents such a mapping framework from the aspect of architecture evaluation. Under this framework, we present two strategies accordingly: The first tends to put highly communicating tasks together. The second is opposite, which aims at SNN features to achieve a balanced distribution of neurons according to their active degrees; for communication-intensive and unbalanced SNNs, this one can alleviate NoC congestion and improve the simulation speed more. This framework also contains a customized NoC simulator to evaluate mapping strategies. Results show that our strategies can achieve a higher simulation speed (up to 1.37 times), and energy consumptions can be reduced or rise very limited.

[1]  Santanu Chattopadhyay,et al.  An Application Mapping Technique for Butterfly-Fat-Tree Network-on-Chip , 2011, 2011 Second International Conference on Emerging Applications of Information Technology.

[2]  José Duato,et al.  Efficient unicast and multicast support for CMPs , 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.

[3]  Yong Liu,et al.  A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[4]  Steve B. Furber,et al.  Population-based routing in the SpiNNaker neuromorphic architecture , 2012, The 2012 International Joint Conference on Neural Networks (IJCNN).

[5]  C. Eliasmith,et al.  Learning to Select Actions with Spiking Neurons in the Basal Ganglia , 2012, Front. Neurosci..

[6]  Xin Jin,et al.  Parallel simulation of neural networks on SpiNNaker universal neuromorphic hardware , 2010 .

[7]  Massoud Pedram,et al.  Application mapping for express channel-based networks-on-chip , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[8]  Suleyman Tosun.  Cluster-based application mapping method for Network-on-Chip , 2011, Adv. Eng. Softw..

[9]  Liam McDaid,et al.  Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware Implementations , 2013, IEEE Transactions on Parallel and Distributed Systems.

[10]  Gerard J. M. Smit,et al.  Fixed latency on-chip interconnect for hardware spiking neural network architectures , 2013, Parallel Comput..

[11]  Saurabh Dighe,et al.  The 48-core SCC Processor: the Programmer's View , 2010, 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis.

[12]  Chris Eliasmith,et al.  A Controlled Attractor Network Model of Path Integration in the Rat , 2005, Journal of Computational Neuroscience.

[13]  René Schüffny,et al.  A graph theoretical approach for a multistep mapping software for the FACETS project , 2008 .

[14]  Nicholas T. Carnevale,et al.  Simulation of networks of spiking neurons: A review of tools and strategies , 2006, Journal of Computational Neuroscience.

[15]  Rodrigo Alvarez-Icaza,et al.  Neurogrid: A Mixed-Analog-Digital Multichip System for Large-Scale Neural Simulations , 2014, Proceedings of the IEEE.

[16]  Sander M. Bohte,et al.  Computing with Spiking Neuron Networks , 2012, Handbook of Natural Computing.

[17]  Stefan Philipp,et al.  Interconnecting VLSI Spiking Neural Networks Using Isochronous Connections , 2007, IWANN.

[18]  Bernard Brezzo,et al.  TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[19]  P. Redgrave,et al.  The basal ganglia: a vertebrate solution to the selection problem? , 1999, Neuroscience.

[20]  Chris Eliasmith,et al.  Neural Engineering: Computation, Representation, and Dynamics in Neurobiological Systems , 2004, IEEE Transactions on Neural Networks.

[21]  Valentin Puente,et al.  MRR: Enabling fully adaptive multicast routing for CMP interconnection networks , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[22]  Natalie D. Enright Jerger,et al.  Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support , 2008, 2008 International Symposium on Computer Architecture.

[23]  Farnood Merrikh-Bayat,et al.  Training and operation of an integrated neuromorphic network based on metal-oxide memristors , 2014, Nature.

[24]  Kwabena Boahen,et al.  Dynamical System Guided Mapping of Quantitative Neuronal Models Onto Neuromorphic Hardware , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

[25]  Jim D. Garside,et al.  Overview of the SpiNNaker System Architecture , 2013, IEEE Transactions on Computers.

[26]  Henry Hoffmann,et al.  On-Chip Interconnection Architecture of the Tile Processor , 2007, IEEE Micro.

[27]  Andrew S. Cassidy,et al.  A million spiking-neuron integrated circuit with a scalable communication network and interface , 2014, Science.

[28]  Christos Strydis,et al.  Optimal mapping of inferior olive neuron simulations on the Single-Chip Cloud Computer , 2014, 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV).

[29]  Santanu Chattopadhyay,et al.  Extending Kernighan-Lin partitioning heuristic for application mapping onto Network-on-Chip , 2014, J. Syst. Archit..

[30]  Marc-Oliver Gewaltig,et al.  Efficient Parallel Simulation of Large-Scale Neuronal Networks on Clusters of Multiprocessor Computers , 2007, Euro-Par.

[31]  G. E. Alexander,et al.  Functional architecture of basal ganglia circuits: neural substrates of parallel processing , 1990, Trends in Neurosciences.

[32]  Chris Eliasmith,et al.  Population Models of Temporal Differentiation , 2010, Neural Computation.

[33]  Andrew S. Cassidy,et al.  Cognitive computing programming paradigm: A Corelet Language for composing networks of neurosynaptic cores , 2013, The 2013 International Joint Conference on Neural Networks (IJCNN).

[34]  Ran Ginosar,et al.  Scalable network-on-chip architecture for configurable neural networks , 2011, Microprocess. Microsystems.