Expert system to configure global design for testability structure in a VLSI circuit

Abstract The paper deals with the problem of design for testability (DFT) in VLSI circuits. An expert system based on currently available knowledge-based system (KBS) technology has been proposed to tackle the problem. The KBS approach has been supported adequately by writing algorithmic procedures specific for each subset of the overall design problem for which a solution can be formalized with well-defined logic. The system identifies the DFT structures necessary to testing various modules of the VLSI circuit. Next, such structures are configured on the circuit by modifying available circuit resources while minimizing logic area overhead, performance degradation and overall test time for the circuit.