A high density 4 kA/cm/sup 2/ Nb integrated circuit process

We have developed an improved 4 kA/cm/sup 2/ process technology that allows a significant increase in circuit speed and density. Improved photoresist and dry etch processes have reduced critical dimension (CD) variation and improved CD linearity to below 1 /spl mu/m. These improvements have enabled a substantial reduction in feature size and full utilization of existing photolithography and etch tools. We have demonstrated mire pitch of 2.0 /spl mu/m with less than 0.1 /spl mu/m CD loss. Minimum junction diameter and contact are 1.75 /spl mu/m and 1.0 /spl mu/m, respectively. Junctions, fabricated using a new barrier oxidation method with improved pressure control, have excellent I-V characteristics and array I/sub c/ nonuniformity less than 1.6% (1/spl sigma/). We have demonstrated a 200 GHz, 12-stage divider circuit that is the fastest complex digital superconductor integrated circuit fabricated to date. With the present process tools, defects are the limiting factor to further increases in circuit density and yield. In this paper, we discuss process improvements, electrical performance, defect reduction, and circuit performance.