A peak efficiency tracking technique to improve the efficiency of switched capacitor DC–DC converters

In this paper, a peak efficiency tracking technique to improve the efficiency of switched capacitor (SC) DC–DC converters as the load varies is presented. A peak efficiency tracking circuit based on feedback control over the switching frequency is implemented for this scope. The basic idea of the proposed technique is to adjust the switching frequency according to the load. The technique is successfully implemented in a SC DC–DC converter to be embedded in detector pixels for the Large Hadron Collider (LHC) experiment at the Conseil Europeen pour la Recherche Nucleaire (CERN) of Geneve. It is realized in 65 nm bulk CMOS technology with an occupied area of 1.31 mm2. This converter provides an 800 mV output voltage from a 1.2 V supply. The load of the DC–DC converters is modeled as a resistor, RLOAD, that has 4 Ω nominal value but it can range from 2.67 up to 10 Ω. At 10 Ω RLOAD, a 6% efficiency improvement is reached with respect to the typical approach consisting in keeping constant the switching frequency at the optimum value for RLOAD nominal value.