Radiation hardened by design techniques to reduce single event transient pulse width based on the physical mechanism
暂无分享,去创建一个
Bin Liang | Shuming Chen | Jianjun Chen | Biwei Liu | Fanyu Liu | Shuming Chen | Jianjun Chen | Bin Liang | Biwei Liu | Fanyu Liu
[1] B.L. Bhuva,et al. Design Techniques to Reduce SET Pulse Widths in Deep-Submicron Combinational Logic , 2007, IEEE Transactions on Nuclear Science.
[2] W. T. Holman,et al. Effects of Guard Bands and Well Contacts in Mitigating Long SETs in Advanced CMOS Processes , 2007, IEEE Transactions on Nuclear Science.
[3] B L Bhuva,et al. Independent Measurement of SET Pulse Widths From N-Hits and P-Hits in 65-nm CMOS , 2010, IEEE Transactions on Nuclear Science.
[4] B.L. Bhuva,et al. RHBD techniques for mitigating effects of single-event hits using guard-gates , 2005, IEEE Transactions on Nuclear Science.
[5] J. Melinger,et al. Investigation of the Propagation Induced Pulse Broadening (PIPB) Effect on Single Event Transients in SOI and Bulk Inverter Chains , 2008, IEEE Transactions on Nuclear Science.
[6] G. Wirth,et al. Single Event Transients in Logic Circuits—Load and Propagation Induced Pulse Broadening , 2008, IEEE Transactions on Nuclear Science.
[7] B.L. Bhuva,et al. Charge Collection and Charge Sharing in a 130 nm CMOS Technology , 2006, IEEE Transactions on Nuclear Science.
[8] P. Eaton,et al. Soft error rate mitigation techniques for modern microcircuits , 2002, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320).
[9] B. Narasimham,et al. The Effectiveness of TAG or Guard-Gates in SET Suppression Using Delay and Dual-Rail Configurations at 0.35 $\mu$ m , 2006, IEEE Transactions on Nuclear Science.
[10] B.L. Bhuva,et al. Laser Verification of Charge Sharing in a 90 nm Bulk CMOS Process , 2009, IEEE Transactions on Nuclear Science.
[11] B. Narasimham,et al. Quantifying the Effect of Guard Rings and Guard Drains in Mitigating Charge Collection and Charge Spread , 2008, IEEE Transactions on Nuclear Science.
[12] peixiong zhao,et al. Scaling Trends in SET Pulse Widths in Sub-100 nm Bulk CMOS Processes , 2010, IEEE Transactions on Nuclear Science.
[13] B L Bhuva,et al. The Effect of Layout Topology on Single-Event Transient Pulse Quenching in a 65 nm Bulk CMOS Process , 2010, IEEE Transactions on Nuclear Science.