Research on SoC test Compression
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[1] Nur A. Touba,et al. Survey of Test Vector Compression Techniques , 2006, IEEE Design & Test of Computers.
[2] Liang Hua. Efficient Test Data Compression and Decompression Based on Alternation and Run Length Codes , 2004 .
[3] Minesh B. Amin,et al. Efficient compression and application of deterministic patterns in a logic BIST architecture , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[4] Xiaowei Li,et al. Co-optimization for test data compression and testing power based on variable-tail code , 2003, ASICON 2003.
[5] Christos A. Papachristou,et al. Multiscan-based test compression and hardware decompression using LZ77 , 2002, Proceedings. International Test Conference.
[6] Erik H. Volkerink,et al. Efficient seed utilization for reseeding based compression [logic testing] , 2003, Proceedings. 21st VLSI Test Symposium, 2003..
[7] Dong Jie,et al. A Multiple-Scan-Chain Test Approach Based on Combinational Decompression Circuits , 2006 .
[8] Li Kang. A Hybrid Run-Length Coding for Soc Test Data Compression , 2005 .
[9] Subhasish Mitra,et al. Efficient Seed Utilization for Reseeding based Compression , 2003 .
[10] Nur A. Touba,et al. Test vector decompression via cyclical scan chains and its application to testing core-based designs , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).
[11] Li Hua-wei. Test Resource Partitioning Using Variable-Tail Code , 2004 .
[12] Krishnendu Chakrabarty,et al. Test Data Compression and Test Resource Partitioning for System-on-a-Chip Using Frequency-Directed Run-Length (FDR) Codes , 2003, IEEE Trans. Computers.
[13] Krishnendu Chakrabarty,et al. System-on-a-chip test-data compression and decompressionarchitectures based on Golomb codes , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..