Successive Approximation A/D Converter for Wireless Sensor Network SoC

A 10-bit 150 kS/s successive approximation A/D converter(ADC) was designed for wireless sensor network SoC.By using offset cancellation,optimized time-sequence control logic and proper layout design,high precision and low power were achieved for the circuit with 0.54 LSB of INL and 0.8 LSB of DNL.When operating at a sampling rate of 150 kS/s with 14.3 kHz input signal,the ADC had an SNR of 60.8 dB and an SFDR of 83.1 dB.Implemented in TSMC's 0.18 μm mixed signal CMOS technology,the IP core occupies a chip area of 0.083 mm2 and the circuit consumes 0.56 mW of power from 1.8 V supply voltage.