A signal folding neural amplifier exploiting neural signal statistics

A novel amplifier for neural recording applications that exploits the 1/fn characteristics of neural signals is described in this paper. Comparison and reset circuits are implemented with the core amplifier to fold a large output waveform into a preset range enabling the use of an ADC with less number of bits for the same effective dynamic range. This also reduces the transmission data rate of the recording chip. Both of these features allow power and area savings at the system level. At the receiver, a reconstruction algorithm is applied in the digital domain to recover the amplified signal from the folded waveform. Other features of this proposed amplifier are increased reliability due to removal of pseudo-resistors, less distortion and low-voltage operation. Meaφsurement results from a 65nm CMOS implementation of a prototype are presented.

[1]  Kristofer S. J. Pister,et al.  An ultralow-energy ADC for Smart Dust , 2003, IEEE J. Solid State Circuits.

[2]  Mohsen Mollazadeh,et al.  Spatiotemporal Variation of Multiple Neurophysiological Signals in the Primary Motor Cortex during Dexterous Reach-to-Grasp Movements , 2011, The Journal of Neuroscience.

[3]  Reid R. Harrison,et al.  A low-power, low-noise CMOS amplifier for neural recording applications , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[4]  R.R. Harrison,et al.  A Low-Power Integrated Circuit for a Wireless 100-Electrode Neural Recording System , 2006, IEEE Journal of Solid-State Circuits.

[5]  Timothy Denison,et al.  Integrated circuit amplifiers for multi-electrode intracortical recording , 2009, Journal of neural engineering.

[6]  Rahul Sarpeshkar,et al.  An Energy-Efficient Micropower Neural Recording Amplifier , 2007, IEEE Transactions on Biomedical Circuits and Systems.

[7]  Scott K. Arfin,et al.  Low-Power Circuits for Brain-Machine Interfaces , 2007, 2007 IEEE International Symposium on Circuits and Systems.