Towards hardware implementation of bzip2 data compression algorithm

Digital architecture dedicated to bzip2 data compression algorithm is proposed. The full functionality of 3 steps of bzip2 - Burrows-Wheeler transform (BWT), Move to front and Huffman coding was achieved for data blocks of 64 hexadecimal characters. Series of logic devices - coders, finite state machines, was implemented in VHDL, verified and synthesized for FPGA. Implementation of Bitonic sort algorithm appeared to be the most difficult and critical part of the design.

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