In the latest ITRS roadmap updated in July 2010, Maskless remains identified as one of the candidate to address lithography needs for the sub-16nm technology nodes. The attractiveness of this solution in terms of cost and flexibility linked to the throughput potential of the massively parallel writing solutions maintain the interest of large scale IC manufacturers, such as TSMC(1) and STMicroelectronics, to push the development of this technology. In July 2009, LETI and MAPPER have initiated an open collaborative program IMAGINE focused on the assessment of the MAPPER technology. This paper reports on the key results obtained during this first assessment year in terms of: resolution capabilities, stitching performances, technology reliability and infrastructure development. It also provides an extensive overview on the maturity degree and the ability of this low energy accelerating voltage multibeam option to answer to the industry needs in the 2015 horizon.