Reliability analysis of combinational circuits with the influences of noise and single-event transients

Noise-immunity is an important design criterion with CMOS dimension scaling to nanometers. Furthermore, nanometer circuits devices are also more prone to soft errors induced by single event transients (SETs). In this work, we set up a model to analyze the reliability induced by both SETs and noise. We derive the constraints for the reliability enhancement of logic circuits for allowing design circuits with both better noise-immunity and higher tolerance to soft errors. Simulation combining Hspice and Matlab are given to verify the proposed constraints.

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