Timing optimization on mapped circuits

This paper describes new techniques for timing optimization of CMOS or BiCMOS gate array or standard cell circuits. Based on previous works on critical path resynthsis, technolo y mapping algorithms using dynamic programming tecfmiques, and fanout optimization algorithms, the following new techniques were developed: a hierarchical data structure in which a circuit is partitioned into subcircuits, a new weight function to grade subcircuits in terms of their potential for delay reduction, a critical path resynthesis technique preceded by non critical path resynthsk, a mapping algorithm using tree covering techniques tightly coupled with a fanout optimization algorithm which can treat dual signals not only in sinks but also in sources, and a correction procedure for short paths. A program using these techniques achieves an average speed up of 37% with 27% increase in area on the DAC'86 benchmark set plus several additional circuits from actual designs.