Implementation of Multi-rate Viterbi Decoder on FPGA

As a result of variable-rate vocoder, the algorithm of multi-rate Viterbi decoder should be introduced in CDMA mobile communication system. By using FPGA of Altera company, a serial multi-rate Viterbi decoder is realized with some optimize astifice, such as full/short tracing back, splitting memories, pipelining control etc., which leads to the advantage of low occupancy of FPGA memories, low delay of hard processing, and high utilization efficiency of FPGA.