Investigation of NBTI and PBTI induced aging in different LUT implementations

Transistor aging mostly due to Negative and Positive Bias Temperature Instability (NBTI and PBTI) is a major reliability threat for VLSI circuits fabricated in nanometer technology nodes. These phenomena can shift the threshold voltage of transistor over time, increase their delays and cause timing failure and ultimately reduction of lifetime of VLSI chips. As much as FPGAs benefit from the most scaled and advanced technologies, they become susceptible to transistor aging. In this paper, we investigate the effect of transistor aging, due to NBTI and PBTI, in look-up tables (LUTs), by considering different implementations through detailed SPICE simulations. We found out that the delay degradation due to transistor aging depends on the mapped configuration, usage (input signal probability) as well as the specific LUT implementation. Moreover, the specific configuration mapped previously into an LUT has a considerable effect on the delay degradation of the currently used configuration of that LUT. We also found that the all-zero configuration which is normally used as the standby configuration is not the best choice and it may even result in high delay degradation.