A 3V robust high-speed low input impedance CMOS current comparator

A simple high-speed low input impedance CMOS current comparator is proposed. The circuit uses improved Wilson current-mirror to perform a subtraction. Negative feedback is employed to reduce the input impedance of the circuit. HSPICE is used to verify the circuit performance with a standard 0.5/spl mu/m CMOS technology. Simulation results demonstrate the propagation delay of 1.02 ns, average power consumption of 0.911 mW and input impedance of 137 /spl Omega/ for /spl plusmn/0.1/spl mu/A input current at the supply voltage of 3V.

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