STATIC RANDOM ACCESS MEMORY USING QUATERNARY D LATCH

In this paper, the implementation of a static random access memory cell using quaternary logic is presented. This static RAM is based on quaternary D latch. When the select line is asserted, the stored data is placed on the cell’s output. When both select and write are asserted the D latch is open and a new data bit is stored. The D latch used here is built using NMAX, NMIN and quaternary inverter circuits. A 4x4 memory array have also been designed and compared with 4x4 array of Quaternary Static CMOS memory Cell.. The spice coding is done using 0.18μm CMOS technology and verification of the design is done through HSPICE and COSMOSSCOPE Synopsis Tools. Power and delay of the circuit is analyzed. New design shows 65.28% of improvement in average power dissipation when compared to 4x4 array of Quaternary Static CMOS memory Cell and 75% improvement over binary 4X4 array at 180nm.

[1]  Kenneth C. Smith.  The Prospects for Multivalued Logic: A Technology and Applications View , 1981, IEEE Transactions on Computers.

[2]  D.A. Rich,et al.  A four-state ROM using multilevel process technology , 1984, IEEE Journal of Solid-State Circuits.

[3]  R.E. Howard,et al.  A programmable analog neural network chip , 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.

[4]  X. Wu,et al.  Ternary CMOS sequential circuits , 1988, [1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic.

[5]  Daniel Etiemble,et al.  Comparison of binary and multivalued ICs according to VLSI criteria , 1988, Computer.

[6]  Michel Verleysen,et al.  Neural networks for high-storage content-addressable memory: VLSI circuit and learning algorithm , 1989 .

[7]  V. Hu,et al.  EEPROM device as a reconfigurable analog element for neural networks , 1989, International Technical Digest on Electron Devices Meeting.

[8]  B. Hochet,et al.  Multivalued MOS memory for variable-synapse neural networks , 1989 .

[9]  J. J. Paulos,et al.  Artificial neural networks using MOS analog multipliers , 1990 .

[10]  G. S. Visweswaran,et al.  Quaternary logic circuits in 2- mu m CMOS technology , 1990 .

[11]  Daniele D. Caviglia,et al.  Selfrefreshing analogue memory cell for variable synaptic weights , 1991 .

[12]  Atsushi Iwata,et al.  Characteristics of floating gate device as analogue memory for neural networks , 1991 .

[13]  D A Durfee,et al.  Comparison of floating gate neural network memory cells in standard VLSI CMOS technology , 1992, IEEE Trans. Neural Networks.

[14]  H. Shinohara,et al.  A refreshable analog VLSI neural network chip with 400 neurons and 40 K synapses , 1992 .

[15]  Lawrence D. Jackel,et al.  Application of the ANNA neural network chip to high-speed character recognition , 1992, IEEE Trans. Neural Networks.

[16]  Chung-Yu Wu,et al.  Design and application of pipelined dynamic CMOS ternary logic and simple ternary differential logic , 1993 .

[17]  José Luis Huertas,et al.  A CMOS analog adaptive BAM with on-chip learning and weight refreshing , 1993, IEEE Trans. Neural Networks.

[18]  Takeshi Sakata,et al.  A single 1.5-V digital chip for a 106 synapse neural network , 1993, IEEE Trans. Neural Networks.

[19]  Takashi Morie,et al.  An all-analog expandable neural network LSI with on-chip backpropagation learning , 1994, IEEE J. Solid State Circuits.

[20]  K. W. Current,et al.  Voltage-mode CMOS quaternary latch circuit , 1994 .

[21]  K. Wayne Current.  Memory circuits for multiple valued logic voltage signals , 1995, Proceedings 25th International Symposium on Multiple-Valued Logic.

[22]  Tadashi Shibata,et al.  A neuron-MOS neural network using self-learning-compatible synapse circuits , 1995, IEEE J. Solid State Circuits.

[23]  Marwan A. Jabri,et al.  A hybrid analog and digital VLSI neural network for intracardiac morphology classification , 1995 .

[24]  Ronald S. Gyurcsik,et al.  Toward a general-purpose analog VLSI neural network with on-chip learning , 1997, IEEE Trans. Neural Networks.

[25]  Thanos Stouraitis,et al.  Design methodology of multiple-valued logic voltage-mode storage circuits , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[26]  Ki-Whan Song,et al.  Complementary self-biased scheme for the robust design of CMOS/SET hybrid multi-valued logic , 2003, 33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings..

[27]  S. Mahapatra,et al.  Realization of multiple valued logic and memory by hybrid SETMOS architecture , 2005, IEEE Transactions on Nanotechnology.

[28]  L. Carro,et al.  A novel Voltage-mode CMOS quaternary logic design , 2006, IEEE Transactions on Electron Devices.

[29]  Vasundara Patel K.S.,et al.  Quaternary CMOS Combinational Logic Circuits , 2009, 2009 International Conference on Information and Multimedia Technology.