Efficient code size reduction without performance loss

For many embedded applications, program code size is a critical design factor for its relationship with limited memory, energy and communication bandwidth. While pursuing better code redundancy elimination in compilation time, people also began to focus on better encoding. Some RISC processors, such as ARM, MIPS and UniCore, support a 32bit/16bit dual-width instruction set. Mixed code generation is introduced in expectation of achieving both higher code density from the 16-bit instruction set and good performance from the 32-bit one, with little extra cost. We describe a new fine-grained mixed code generation scheme in this paper. We introduce into the 32-bit ISA a new 16-bit Mode-Changing instruction set which has the following features: firstly, the operation of the instructions are very common in UniCore32 programs and are appropriate to be coded into 16 bits; secondly, they can switch the current processor mode while performing their own operations. We implement the mixed code generation at link time in our compilation toolchain. Our experiments show that this scheme is successful in better encoding a program's computations to reduce code size without sacrificing performance. In addition, there are little modifications to micro-architecture, ensuring good compatibility with the original instruction set architecture.

[1]  Liam Goudge,et al.  Thumb: reducing the cost of 32-bit RISC performance in portable and consumer applications , 1996, COMPCON '96. Technologies for the Information Superhighway Digest of Papers.

[2]  Donald S. Fussell,et al.  16-bit vs. 32-bit instructions for pipelined microprocessors , 1993, ISCA '93.

[3]  Hyuk-Jae Lee,et al.  PARE: instruction set architecture for efficient code size reduction , 1999 .

[4]  Sang Lyul Min,et al.  Code Generation for a Dual Instruction Set Processor Based on Selective Code Transformation , 2003, SCOPES.

[5]  Rajiv Gupta,et al.  Profile guided selection of ARM and thumb instructions , 2002, LCTES/SCOPES '02.

[6]  Rajiv Gupta,et al.  Enhancing the performance of 16-bit code using augmenting instructions , 2003 .

[7]  Rajiv Gupta,et al.  Efficient use of invisible registers in Thumb code , 2005, 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'05).

[8]  Miodrag Potkonjak,et al.  MediaBench: a tool for evaluating and synthesizing multimedia and communications systems , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.

[9]  Richard Phelan Improving ARM Code Density and Performance , 2003 .

[10]  Aviral Shrivastava,et al.  An efficient compiler technique for code size reduction using reduced bit-width ISAs , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[11]  Todd M. Austin,et al.  The SimpleScalar tool set, version 2.0 , 1997, CARN.