Enhancing the area-efficiency of FPGAs with hard circuits using shadow clusters

There is a dramatic logic density gap between FPGAs and ASICs, and this gap is the main reason FPGAs are not cost-effective in high volume applications. Modern FPGAs narrow this gap by including "hard" circuits such as memories and multipliers, which are very efficient when they are used. However, if these hard circuits are not used, they go wasted (including the very expensive programmable routing that surrounds the logic) and have a negative impact on logic density. In this paper we propose a new architectural concept, called shadow clusters, that seeks to mitigate this loss. A shadow cluster is a standard FPGA logic "cluster" that is placed "behind" every hard circuit and can programmably, through simple, small multiplexers, replace the hard circuit in the event it isn't needed. The authors measure the area-efficiency of FPGAs with and without shadow clusters and show that a modern commercial architecture (with a fixed ratio of multipliers to soft logic) would gain 4.7% in area-efficiency by employing shadow clusters. Indeed, every architecture we studied under "reasonable" conditions never showed a loss of area-efficiency. Furthermore, we show that most area-efficient architecture that employs the shadow cluster concept is 12.5 % better than the most area-efficient architecture without shadow clusters