A study of compact thermal model topologies in CFD for a flip chip plastic ball grid array package

A previously validated detailed model of a 119-pin Flip-Chip Plastic Ball Grid Array (FC-PBGA) package was created and validated against experimental data for natural convection and forced convection environments. Next, two compact models were derived, a two-resistor model (created using the JEDEC-standard based computational approach), and a multi-resistor model (created using the DELPHI optimization approach that was boundary condition independent within engineering accuracy). The compact models were placed in natural convection and forced convection (velocities of 1 and 2 m/s) environments with and without a heatsink. Based on the agreement obtained between the detailed model and compact model simulations, the accuracy and validity of the two compact models was assessed. Of the two compact thermal models considered, the Delphi multi-resistor model provided the same predictive estimates (within 5%) as simulations involving a detailed thermal model of the package in natural and forced convection environments both with and without attached heatsinks. Some thermal modeling issues were addressed with respect to implementation of compact thermal models with attached heatsinks.

[1]  Sarang Shidore,et al.  A Comparative Study of the Performance of Compact Model Topologies and Their Implementation in CFD for a Plastic Ball Grid Array Package , 2001 .

[2]  K. Ramakrishna,et al.  Thermal sub-modeling of the wirebonded plastic ball grid array package , 1997, Thirteenth Annual IEEE. Semiconductor Thermal Measurement and Management Symposium.

[3]  F. Kreith,et al.  Principles of heat transfer , 1962 .

[4]  H. I. Rosten.  DELPHI-a status report on the European-funded project for the development of libraries and physical models for an integrated design environment , 1996, 1996 Proceedings 46th Electronic Components and Technology Conference.

[5]  B. Joiner,et al.  Measurement and simulation of junction to board thermal resistance and its application in thermal modeling , 1999, Fifteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.99CH36306).

[6]  V. B. Dutta.  Junction-to-case thermal resistance-still a myth? , 1988, Fourth Annual IEEE Semiconductor Thermal and Temperature Measurement Symposium.

[7]  P. Stehouwer,et al.  Creation and evaluation of compact models for thermal characterisation using dedicated optimisation software , 1999, Fifteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.99CH36306).

[8]  G. B. Kromann,et al.  The development of component-level thermal compact models of a C4/CBGA interconnect technology: the Motorola PowerPC 603/sup TM/ and PowerPC 604/sup TM/ RISC microprocessors , 1996, 1996 Proceedings 46th Electronic Components and Technology Conference.