Area Efficient Methods to Increase the Reliability of Circuits

We consider the problem to construct reliable combinatorial and clocked circuits from unreliable basic elements. The main concern in this paper is the question how such fault-tolerance increases the circuit layout. In general it requires at least a logarithmic factor increase of the number of gates. We design area efficient codes for the information transfer within a Boolean circuit. Using such a code two constructions are presented to make circuits reliable without increasing the area by a square of the redundancy overhead for their sizes. The first method splits the circuit into clusters and connects the clusters reliably by groups of wires. As an alternative, a recursive layout stratey for circuits is described which uses special graph separator properties. Under certain conditions it achieves only a constant blowup of the area compared to circuits built from completely reliable elements.