Modeling speculative execution and availability analysis with Boolean expressions

Emerging design problems are prompting the use of instruction-level parallelism techniques during the high-level synthesis (HLS) of ASICs or ASIPs in order to meet tight time-constraints. Techniques like code motion and speculative execution can grant time-constraint satisfiability because they can shorten schedule lengths. The mechanism for inducing code motion and speculative execution relies on the global computation of the operations available for scheduling at a given state. This is called availability analysis. We propose an availability analysis technique that captures major achievements from the compiler domain while keeping one of the most popular HLS representations, namely, the data-flow graph. The key is to combine graph manipulation for keeping track of data dependences with Boolean techniques for dealing with conditional execution. An important practical aspect of our Boolean modeling of conditional execution is that public-domain packages for Boolean manipulation are widely available in the design automation community. Therefore, our formulation holds the promise of allowing existent HLS tools to benefit from global scheduling at the expense of a few extensions. The technique is currently used within a prototype tool. Experiments performed on classical examples from the HLS literature show that our technique reaches the best published results. Keywords—high-level synthesis, code generation, scheduling, code motion, speculative execution.