A Hardware Evaluation Study of NIST Post-Quantum Cryptographic Signature schemes

As we are moving into the quantum era, classical cryptography is under risk, since quantum computers can break these complex cryptographic algorithms [1]. Researchers are developing the post-quantum cryptographic (PQC) algorithms to secure the system against quantum computers. The National Institute of Standards and Technology (NIST) started a public evaluation process to standardize quantum-resistant public key algorithms. The objective of this study to provide hardware-based comparison of the NIST Round-2 PQC signature schemes. For this, we use a High-Level Synthesis (HLS)-based hardware design methodology to map high-level C specifcations of signature-based PQC algorithms into FPGA implementations.