Hybrid trace back apparatus and high-speed viterbi decoding system using it

1. the art that the invention defined in the claims The present invention will on the high speed Viterbi decoding system with him and hybrid traceback unit. 2. The invention attempts to solve the technical challenges The present invention in hardware, using the structure of the fully parallel ACS, and in the structure using radix4 instead radix2 for optimization of the critical path, applying the hybrid method that combines the register exchange scheme and traceback methods in order to perform a high-speed communication that aims to provide a high-speed Viterbi decoding system with improved performance and the size and power consumption to provide the optimized structure hybrid traceback in the apparatus and him. 3. Resolution of the subject matter of the invention, The present invention, the register exchange means for receiving the branches (survivor path) of the path metrics from the path metric calculator, to obtain the block survival value through the register exchange by the bit length to the block traceback; The register exchange stores the block survival value so smoothly and output, and storage means for storing, until the block survival values ​​obtained through the register exchange block written to the traceback memory; And comprising a block backtracking means for outputting the decoded data by performing a block inverse track by writing the value of the storage means to the block traceback memory, having a full parallel ACS (Add Compare Select) structure with Radix4 It characterized. 4. An important use of the invention, The invention yiyongdoem like high-speed wireless communication system. Hybrid traceback, the register exchange, the traceback block, Viterbi decoder, Radix4