Low power clock buffer planning methodology in F-D placement for large scale circuit design
暂无分享,去创建一个
[1] Lawrence T. Pillage,et al. Skew And Delay Optimization For Reliable Buffered Clock Trees , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).
[2] Wayne Wei-Ming Dai,et al. Buffer insertion and sizing under process variations for low power clock distribution , 1995, DAC '95.
[3] Jason Cong,et al. Bounded-skew clock and Steiner routing , 1998, TODE.
[4] Frank M. Johannes,et al. Generic global placement and floorplanning , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[5] Jiang Hu,et al. A Placement Methodology for Robust Clocking , 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).
[6] Subhrajit Bhattacharya,et al. Keeping hot chips cool , 2005, Proceedings. 42nd Design Automation Conference, 2005..
[7] Jiang Hu,et al. Buffered clock tree for high quality IC design , 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).
[8] Lei He,et al. Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-Flop Insertion , 2003, ICCAD 2003.
[9] Chung-Kuan Cheng,et al. Optimal buffered clock tree synthesis , 1994, Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit.
[10] Adnan Aziz,et al. Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion , 2000, ISPD '00.
[11] Wei Li,et al. Buffer insertion for clock delay and skew minimization , 1999, ISPD '99.
[12] Yao-Wen Chang,et al. Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation , 1996, 33rd Design Automation Conference Proceedings, 1996.
[13] Martin D. F. Wong,et al. An algorithm for zero-skew clock tree routing with buffer insertion , 1996, Proceedings ED&TC European Design and Test Conference.
[14] Andrew A. Kennings,et al. Engineering details of a stable force-directed placer , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..
[15] Yongqiang Lyu,et al. Navigating registers in placement for clock network minimization , 2005, Proceedings. 42nd Design Automation Conference, 2005..
[16] Andrew B. Kahng,et al. Power-aware placement , 2005, Proceedings. 42nd Design Automation Conference, 2005..