High-Voltage CMOS ESD and the Safe Operating Area

Established methods for testing ESD robustness of high-voltage pins in smart power CMOS can lead to erroneous results. This paper investigates both LDNMOS and certain types of SCRLDMOS (SCRs embedded in LDNMOS) high-voltage clamps for safe-operating-area collapse due to trigger voltage (V t1) walk-in after transmission-line pulsing (TLP) corresponding to leakage-current increase below I t2. For the first time, the evolution of V t1 as a function of the number of TLP pulses and their magnitude is shown. Furthermore, some high-voltage clamps that are robust on their own are shown to walk-in in certain circuit environments that present high capacitance. The physical mechanism for this leakage enhancement and trigger-voltage walk-in has been established through failure analysis to be consistent with melt filament growth perhaps aided by metal migration. A simple phenomenological model is proposed to explain this behavior. Finally, the ability to avoid such V t1 collapse in SCRLDMOS through simple layout changes is shown.

[1]  R. Y. Shiue,et al.  Novel ESD protection structure with embedded SCR LDMOS for smart power technology , 2002, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320).

[2]  Bart Keppens,et al.  ESD protection solutions for high voltage technologies , 2004 .

[3]  P.L. Hower,et al.  Snapback and safe operating area of LDMOS transistors , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[4]  A. Konrad,et al.  ESD Protection of NDMOS in 0.18μm High-Voltage CMOS Technology for Automotive Applications , 2008, 2008 20th International Symposium on Power Semiconductor Devices and IC's.

[5]  H. C. Poon,et al.  High injection in epitaxial transistors , 1968 .

[6]  H. Puchner,et al.  Novel Robust High Voltage ESD Clamps for LDMOS Protection , 2007, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual.

[7]  D. H. Pontius,et al.  Second breakdown and damage in junction devices , 1973 .

[8]  John C. Fothergill,et al.  Electrical degradation and breakdown in polymers , 1992 .

[9]  Won-Gi Min,et al.  ESD Scalability of LDMOS Devices for Self-Protected Output Drivers , 2005, Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005..

[10]  Wolfgang Fichtner,et al.  Analysis of lateral DMOS power devices under ESD stress conditions , 2000 .

[11]  C. Duvvury,et al.  Lateral DMOS design for ESD robustness , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[12]  Len A. Dissado,et al.  Understanding electrical trees in solids: from experiment to theory , 2001, ICSD'01. Proceedings of the 20001 IEEE 7th International Conference on Solid Dielectrics (Cat. No.01CH37117).

[13]  Jian-Hsing Lee,et al.  The Influence of NBL Layout and LOCOS Space on Component ESD and System Level ESD for HV-LDMOS , 2007, Proceedings of the 19th International Symposium on Power Semiconductor Devices and IC's.

[14]  Ming-Dou Ker,et al.  The Impact of Drift Implant and Layout Parameters on ESD Robustness for On-Chip ESD Protection Devices in 40-V CMOS Technology , 2007, IEEE Transactions on Device and Materials Reliability.

[15]  Jin-Biao Huang,et al.  Current filament movement and silicon melting in an ESD-robust DENMOS transistor , 2003, 2003 Electrical Overstress/Electrostatic Discharge Symposium.

[16]  A. Walker,et al.  Analysis of tungsten and titanium migration during ESD contact burnout , 2003 .

[17]  Taylor R. Efland,et al.  SCR-LDMOS. A novel LDMOS device with ESD robustness , 2000, 12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094).

[19]  V. Parthasarathy,et al.  A double RESURF LDMOS with drain profile engineering for improved ESD robustness , 2002, IEEE Electron Device Letters.

[20]  G. Reimbold,et al.  An attempt to explain thermally induced soft failures during low level ESD stresses: study of the differences between soft and hard NMOS failures. , 1997, Proceedings Electrical Overstress/Electrostatic Discharge Symposium.

[21]  H. Grubin.  The physics of semiconductor devices , 1979, IEEE Journal of Quantum Electronics.

[22]  Michael C. Smayling,et al.  Device integration for ESD robustness of high voltage power MOSFETs , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[23]  B. Baird,et al.  Snapback Breakdown Dynamics and ESD Susceptibility of LDMOS , 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.