1.1 V high speed, low power BiCMOS logic circuit

A 1.1 V full-swing, high speed, low power BiCMOS logic circuit is presented. It consists of nine devices and uses a noncomplementary BiCMOS process. Bootstrapping and partial charge removal techniques are employed. HSPICE simulations have shown that the new circuit outperforms both CMOS and a recently reported circuit in terms of speed and power-delay product. An analytical expression relating the pull-up delay with its device parameters is also derived.