Untidy Evolution: Evolving Messy Gates for Fault Tolerance

The exploitation of the physical characteristics has already been demonstrated in the intrinsic evolution of electronic circuits. This paper is an initial attempt at creating a world in which "physics" can be exploited in simulation. As a starting point we investigate a model of gate-like components with added noise. We refer to this as a kind of messiness. The principal idea behind these messy gates is that artificial evolution makes a virtue of the untidiness. We are ultimately trying to study the question: What kind of components should we use in artificial evolution? Several experiments are described that show that the messy circuits have a natural robustness to noise, as well as an implicit faulttolerance. In addition, it was relatively easy for evolution to generate novel circuits that were surprisingly efficient.

[1]  Adrian Stoica,et al.  Fault-tolerant evolvable hardware using field-programmable transistor arrays , 2000, IEEE Trans. Reliab..

[2]  Marco Tomassini,et al.  A phylogenetic, ontogenetic, and epigenetic view of bio-inspired hardware systems , 1997, IEEE Trans. Evol. Comput..

[3]  Paul J. Layzell,et al.  Evolution of Robustness in an Electronics Design , 2000, ICES.

[4]  Vu Duong,et al.  Evolution of analog circuits on field programmable transistor arrays , 2000, Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware.

[5]  Algirdas Avizienis,et al.  Toward Systematic Design of Fault-Tolerant Systems , 1997, Computer.

[6]  F. M. Miles,et al.  Principles of fault tolerance , 1996, Proceedings of Applied Power Electronics Conference. APEC '96.

[7]  Adrian Thompson,et al.  An Evolved Circuit, Intrinsic in Silicon, Entwined with Physics , 1996, ICES.

[8]  T. R. Damarla,et al.  Fault tolerance of neural networks , 1989, Proceedings. IEEE Energy and Information Technologies in the Southeast'.

[9]  Julian Francis Miller,et al.  Cartesian genetic programming , 2000, GECCO '10.

[10]  Jos Nijhuis,et al.  Limits to the fault-tolerance of a feedforward neural network with learning , 1990, [1990] Digest of Papers. Fault-Tolerant Computing: 20th International Symposium.

[11]  Adrian Thompson,et al.  On the Automatic Design of Robust Electronics Through Artificial Evolution , 1998, ICES.

[12]  B. E. Segee,et al.  Fault tolerance of pruned multilayer networks , 1991, IJCNN-91-Seattle International Joint Conference on Neural Networks.

[13]  Gregory S. Hornby,et al.  Proceedings of the 8th international conference on Evolvable Systems: From Biology to Hardware , 2003 .

[14]  Adrian Thompson,et al.  Hardware evolution - automatic design of electronic circuits in reconfigurable hardware by artificial evolution , 1999, CPHC/BCS distinguished dissertations.