Simple virtual channel allocation for high throughput and high frequency on-chip routers
暂无分享,去创建一个
Jun Yang | Youtao Zhang | Yi Xu | Bo Zhao | Jun Yang | Youtao Zhang | Bo Zhao | Yi Xu
[1] Stamatis Vassiliadis,et al. Design and evaluation of a DAMQ multiprocessor network with self-compacting buffers , 1994, Proceedings of Supercomputing '94.
[2] Chita R. Das,et al. ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).
[3] Ahmed Louri,et al. iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures , 2008, 2008 International Symposium on Computer Architecture.
[4] George Kurian,et al. ATAC: A 1000-core cache-coherent processor with on-chip optical network , 2010, 2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT).
[5] Onur Mutlu,et al. A case for bufferless routing in on-chip networks , 2009, ISCA '09.
[6] Marc Tremblay,et al. Rock: A High-Performance Sparc CMT Processor , 2009, IEEE Micro.
[7] Timothy Mark Pinkston,et al. Evaluation of queue designs for true fully adaptive routers , 2004, J. Parallel Distributed Comput..
[8] José Duato. Deadlock-free adaptive routing algorithms for multicomputers: evaluation of a new algorithm , 1991, Proceedings of the Third IEEE Symposium on Parallel and Distributed Processing.
[9] Krisztián Flautner,et al. PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor , 2006, ASPLOS XII.
[10] William J. Dally,et al. Virtual-channel flow control , 1990, [1990] Proceedings. The 17th Annual International Symposium on Computer Architecture.
[11] Kunle Olukotun,et al. A Single-Chip Multiprocessor , 1997, Computer.
[12] Laxmi N. Bhuyan,et al. Circular buffered switch design with wormhole routing and virtual channels , 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).
[13] William J. Dally,et al. A delay model and speculative architecture for pipelined routers , 2001, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture.
[14] Lei Jiang,et al. Die Stacking (3D) Microarchitecture , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).
[15] A. Kumary,et al. A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS , 2007 .
[16] A. Alvandpour,et al. A 5.1GHz 0.34mm2 Router for Network-on-Chip Applications , 2007, 2007 IEEE Symposium on VLSI Circuits.
[17] Shubhendu S. Mukherjee,et al. The Alpha 21364 network architecture , 2001, HOT 9 Interconnects. Symposium on High Performance Interconnects.
[18] William J. Dally,et al. Deadlock-Free Message Routing in Multiprocessor Interconnection Networks , 1987, IEEE Transactions on Computers.
[19] William J. Dally,et al. A Delay Model for Router Microarchitectures , 2001, IEEE Micro.
[20] Dean M. Tullsen,et al. Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling , 2005, ISCA 2005.
[21] William J. Dally,et al. Flattened Butterfly Topology for On-Chip Networks , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).
[22] William J. Dally,et al. Principles and Practices of Interconnection Networks , 2004 .
[23] Kai Li,et al. The PARSEC benchmark suite: Characterization and architectural implications , 2008, 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT).
[24] Chita R. Das,et al. A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks , 2006, 33rd International Symposium on Computer Architecture (ISCA'06).
[25] Niraj K. Jha,et al. A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS , 2007, ICCD.
[26] Kunle Olukotun,et al. The case for a single-chip multiprocessor , 1996, ASPLOS VII.
[27] Sriram R. Vangal,et al. A 5-GHz Mesh Interconnect for a Teraflops Processor , 2007, IEEE Micro.
[28] Sharad Malik,et al. Power-driven Design of Router Microarchitectures in On-chip Networks , 2003, MICRO.
[29] Jung Ho Ahn,et al. A Comprehensive Memory Modeling Tool and Its Application to the Design and Analysis of Future Memory Hierarchies , 2008, 2008 International Symposium on Computer Architecture.
[30] Saurabh Dighe,et al. An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[31] Niraj K. Jha,et al. Token flow control , 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.
[32] Chita R. Das,et al. A low latency router supporting adaptivity for on-chip interconnects , 2005, Proceedings. 42nd Design Automation Conference, 2005..
[33] Simon W. Moore,et al. Low-latency virtual-channel routers for on-chip networks , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..
[34] William J. Dally,et al. Design tradeoffs for tiled CMP on-chip networks , 2006, ICS '06.
[35] Mike Galles. Spider: a high-speed network interconnect , 1997, IEEE Micro.
[36] Jun Yang,et al. Simple virtual channel allocation for high throughput and high frequency on-chip routers , 2010, HPCA.
[37] Yuval Tamir,et al. High-performance multiqueue buffers for VLSI communication switches , 1988, [1988] The 15th Annual International Symposium on Computer Architecture. Conference Proceedings.
[38] Y. Tamir,et al. High-performance multi-queue buffers for VLSI communications switches , 1988, ISCA '88.
[39] George Michelogiannakis,et al. Elastic-buffer flow control for on-chip networks , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.
[40] Stephen W. Keckler,et al. Regional congestion awareness for load balance in networks-on-chip , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.
[41] Niraj K. Jha,et al. Express virtual channels: towards the ideal interconnection fabric , 2007, ISCA '07.