Toward scalable source level accuracy analysis for floating-point to fixed-point conversion

In embedded systems, many numerical algorithms are implemented with fixed-point arithmetic to meet area cost and power constraints. Fixed-point encoding decisions can significantly affect cost and performance. To evaluate their impact on accuracy, designers resort to simulations. Their high running-time prevents thorough exploration of the design-space. To address this issue, analytical modeling techniques have been proposed, but their applicability is limited by scalability issues. In this paper, we extend these techniques to a larger class of programs. We use polyhedral methods to extract a more compact, graph-based representation of the program. We validate our approach with a several image and signal processing algorithms.

[1]  David Novo,et al.  Accuracy vs speed tradeoffs in the estimation of fixed-point errors on Linear Time-Invariant systems , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[2]  Markus Rupp,et al.  Automated floating-point to fixed-point conversion with the fixify environment , 2005, 16th IEEE International Workshop on Rapid System Prototyping (RSP'05).

[3]  Eric Goubault,et al.  Static Analysis of Finite Precision Computations , 2011, VMCAI.

[4]  Zhigang Chen,et al.  On Uniformization of Affine Dependence Algorithms , 1996, IEEE Trans. Computers.

[5]  Sebastian Hack,et al.  A dynamic program analysis to find floating-point accuracy problems , 2012, PLDI.

[6]  Romuald Rocher,et al.  Analytical Fixed-Point Accuracy Evaluation in Linear Time-Invariant Systems , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[7]  George A. Constantinides,et al.  A scalable approach for automated precision analysis , 2012, FPGA '12.

[8]  Gabriel Caffarena,et al.  SQNR Estimation of Fixed-Point DSP Algorithms , 2010, EURASIP J. Adv. Signal Process..

[9]  Doris Chen,et al.  Profile-guided floating- to fixed-point conversion for hybrid FPGA-processor applications , 2013, TACO.

[10]  V. van Dongen,et al.  Uniformization of linear recurrence equations: a step toward the automatic synthesis of systolic arrays , 1988, [1988] Proceedings. International Conference on Systolic Arrays.

[11]  Seehyun Kim,et al.  Finite wordlength effects analysis and wordlength optimization of a multiplier-adder based 8/spl times/8 2D-IDCT architecture , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[12]  Wayne Luk,et al.  Wordlength optimization for linear digital signal processing , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Wayne Luk,et al.  The Multiple Wordlength Paradigm , 2001, The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01).

[14]  Paul Feautrier,et al.  Dataflow analysis of array and scalar references , 1991, International Journal of Parallel Programming.

[15]  James C. Hoe,et al.  Improving fixed-point accuracy of FFT cores in O-OFDM systems , 2012, 2012 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

[16]  Denis Barthou,et al.  On the Recognition of Algorithm Templates , 2004, COCV@ETAPS.

[17]  George A. Constantinides Perturbation analysis for word-length optimization , 2003, 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003..

[18]  Robert W. Brodersen,et al.  A perturbation theory on statistical quantization effects in fixed-point DSP with non-stationary inputs , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[19]  Sanjay V. Rajopadhye,et al.  On Synthesizing Systolic Arrays from Recurrence Equations with Linear Dependencies , 1986, FSTTCS.

[20]  Patrice Quinton Automatic synthesis of systolic arrays from uniform recurrent equations , 1984, ISCA '84.

[21]  Romuald Rocher,et al.  Analytical Approach for Numerical Accuracy Estimation of Fixed-Point Systems Based on Smooth Operations , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.