Mixed-signal modelling in VHDL for system-on-chip applications

Function transfer based modelling techniques are applied to the IEEE VHDL language to develop behavioral analogue models. This allows mixed-signal simulations integrated into a top-down ASIC design flow for system designers. An application to a clock module for a DSP-core ASIC, integrating a Phase-Locked Loop, demonstrates the usefulness of such an approach for the validation of large systems containing a small portion of analogue functionalities.<<ETX>>