Novel refractory contact and interconnect metallizations for high-voltage and smart-power applications

Power electronic system performance enhancements, device structures, process technologies, manufacturability, and performance results obtained from three distinct process technologies that are based on selective TiSi/sub 2/ and low-pressure chemical vapor deposition (LPCVD) tungsten, and blanket LPCVD WSi/sub 2/ are discussed. Several key factors are identified that should be helpful in the choice and implementation of refractory metallization targeted for a specific system enhancement. It is demonstrated that the application of advanced wafer fabrication technologies using refractory multilevel metallizations has resulted in nearly optimal performance from low-voltage silicon power devices. Tables are shown which summarize the current state of the art of refractory metallization as applied to power system applications. It is seen that TiSi/sub 2/-based technology has the highest potential for near-term commercialization, followed by LPCVD WSi/sub 2/. >

[1]  R. C. Rustay,et al.  Theoretical basis for field calculations on multi-dimensional reverse biased semiconductor devices , 1982 .

[2]  K. Saraswat,et al.  Properties of low-pressure CVD tungsten silicide for MOS VLSI interconnections , 1983, IEEE Transactions on Electron Devices.

[3]  K. Shenai,et al.  Optimally scaled low-voltage vertical power MOSFETs for high-frequency power conversion , 1990 .

[4]  K. Shenai,et al.  Effect of gate resistance on high-frequency power switching efficiencies of advanced power MOSFETs , 1990 .

[5]  K. Shenai,et al.  A 50-V, 0.7-m Omega *cm/sup 2/, vertical-power DMOSFET , 1989, IEEE Electron Device Letters.

[6]  Robert S. Wrathall The design of a high power solid state automotive switch in CMOS-VDMOS technology , 1985, 1985 IEEE Power Electronics Specialists Conference.

[7]  B. Jayant Baliga High-voltage device termination techniques a comparative review , 1982 .

[8]  C. M. Bailey Basic Integrated Circuit Failure Mechanisms , 1982 .

[9]  E. J. Lloyd,et al.  Self-aligned cobalt disilicide for gate and interconnection and contacts to shallow junctions , 1987, IEEE Transactions on Electron Devices.

[10]  M.S. Adler,et al.  The evolution of power device technology , 1984, IEEE Transactions on Electron Devices.

[11]  K. Shenai,et al.  Modeling and characterization of dopant redistributions in metal and silicide contacts , 1985, IEEE Transactions on Electron Devices.

[12]  H. Benz,et al.  Effect of silicon-gate resistance on the frequency response of MOS transistors , 1975, IEEE Transactions on Electron Devices.

[13]  M.S. Adler,et al.  Lateral HVIC with 1200-V bipolar and field-effect devices , 1986, IEEE Transactions on Electron Devices.

[14]  A.K. Sinha,et al.  Speed limitations due to interconnect time constants in VLSI integrated circuits , 1982, IEEE Electron Device Letters.

[15]  W. H. Christie,et al.  Quality solder poste systems for use in microelectronic applications , 1983 .

[16]  D. B. Fraser,et al.  Electromigration Resistance of Fine-Line Al for VLSI Applications , 1980, 18th International Reliability Physics Symposium.

[17]  Chenming Hu,et al.  The operation of power MOSFET in reverse mode , 1983 .

[18]  Accurate barrier modeling of metal and silicide contacts , 1984, IEEE Electron Device Letters.

[19]  M.S. Adler,et al.  Power semiconductor switching devices—A comparison based on inductive switching , 1982, IEEE Transactions on Electron Devices.

[20]  C. Salama,et al.  Nonplanar power field-effect transistors , 1978, IEEE Transactions on Electron Devices.

[21]  P. Ghate,et al.  Electromigration-Induced Failures in VLSI Interconnects , 1982, 20th International Reliability Physics Symposium.

[22]  Krishna C. Saraswat,et al.  Effect of scaling of interconnections on the time delay of VLSI circuits , 1982 .

[23]  P. Galbiati,et al.  A new integrated silicon gate technology combining bipolar linear, CMOS logic, and DMOS power parts , 1986, IEEE Transactions on Electron Devices.