A multi-step standard-cell placement algorithm of optimizing timing and congestion behavior

The timing behavior and congestion behavior are two important goals in the performance-driven standard-cell placement. In this paper, we analyze the relationship between the timing and congestion behavior. We bring up a multi-step placement algorithm to reach the two goals. First, the timing-driven placement algorithm is used to find the global optimal solution. In the second step, the algorithm tries to decrease the maximum congestion while not deteriorating the timing behavior. We have implemented our algorithm and tested it with real circuits. The results show that the maximum delay can decrease by 30% in our timing-driven placement and in the second step the maximum congestion will decrease by 10% while the timing behavior is unchanged.

[1]  Carl Sechen,et al.  Efficient and effective placement for very large circuits , 1993, ICCAD.

[2]  Georg Sigl,et al.  GORDIAN: VLSI placement by quadratic programming and slicing optimization , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Hong Xian A New Timing-Driven Placement Algorithm Based on Table\|Lookup Delay Model\+* , 2000 .

[4]  Yici Cai,et al.  A new congestion-driven placement algorithm based on cell inflation , 2001, ASP-DAC '01.

[5]  Arvind Srinivasan,et al.  RITUAL: a performance driven placement algorithm for small cell ICs , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[6]  Majid Sarrafzadeh,et al.  On the behavior of congestion minimization during placement , 1999, ISPD '99.

[7]  Richard B. Brown,et al.  Congestion driven quadratic placement , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[8]  Carl Sechen,et al.  Efficient and effective placement for very large circuits , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Maogang Wang,et al.  Interaction among cost functions in placement , 1999, ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361).

[10]  Majid Sarrafzadeh,et al.  A delay budgeting algorithm ensuring maximum flexibility in placement , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  E.S. Kuh,et al.  PROUD: a sea-of-gates placement algorithm , 1988, IEEE Design & Test of Computers.

[12]  Majid Sarrafzadeh,et al.  Dragon2000: standard-cell placement tool for large industry circuits , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).