Atomistic nanoelectronic device engineering with sustained performances up to 1.44 PFlop/s

We present a multi-dimensional, atomistic, quantum transport simulation approach to investigate the performances of realistic nanoscale transistors for various geometries and material systems. The central computation consists in solving the Schrodinger equation with open boundary conditions several thousand times. To do that, a Wave Function approach is used since it can be relatively easily parallelized. To further improve the computational efficiency, three additional levels of parallelization are identified, the work load is optimally balanced between the CPUs, computational interleaving is applied where possible, and a mixed precision scheme is introduced. Using two different device types, a high electron mobility and a band-to-band tunneling transistor, sustained performances up to 1.28 PFlop/s in double precision (55% of the peak performance) and 1.44 PFlop/s in mixed precision are reached on 221,400 cores on the CRAY-XT5 Jaguar at Oak Ridge National Lab.

[1]  John B. Shoven,et al.  I , Edinburgh Medical and Surgical Journal.

[2]  G. G. Stokes.  "J." , 1890, The New Yale Book of Quotations.

[3]  J. C. Slater,et al.  Simplified LCAO Method for the Periodic Potential Problem , 1954 .

[4]  W. Kohn,et al.  Self-Consistent Equations Including Exchange and Correlation Effects , 1965 .

[5]  R. Sweet.  A Cyclic Reduction Algorithm for Solving Block Tridiagonal Systems of Arbitrary Dimension , 1977 .

[6]  S. Selberherr,et al.  MINIMOS - A Two-Dimensional MOS Transistor Analyzer , 1980, IEEE Journal of Solid-State Circuits.

[7]  Siegfried Selberherr,et al.  MINIMOS—A two-dimensional MOS transistor analyzer , 1980 .

[8]  W. Fichtner,et al.  Numerical methods for semiconductor device simulation , 1983, IEEE Transactions on Electron Devices.

[9]  W. Fichtner,et al.  Semiconductor device simulation , 1983, IEEE Transactions on Electron Devices.

[10]  Iterative methods in semiconductor device simulation , 1985, IEEE Transactions on Electron Devices.

[11]  Moroni,et al.  Electronic structure of the InAs-GaSb superlattice studied by the renormalization method. , 1989, Physical review. B, Condensed matter.

[12]  Anthony Skjellum,et al.  A High-Performance, Portable Implementation of the MPI Message Passing Interface Standard , 1996, Parallel Comput..

[13]  R. Sani,et al.  Incompressible Flow and the Finite Element Method, Volume 1, Advection-Diffusion and Isothermal Laminar Flow , 1998 .

[14]  G.E. Moore,et al.  Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.

[15]  Patrick R. Amestoy,et al.  Multifrontal parallel distributed symmetric and unsymmetric solvers , 2000 .

[16]  John N. Shadid,et al.  Official Aztec user''s guide: version 2.1 , 1999 .

[17]  T. Cwik,et al.  sp3s* Tight-Binding Parameters for Transport Simulations in Compound Semiconductors , 2000 .

[18]  J. Szmelter.  Incompressible flow and the finite element method , 2001 .

[19]  Jack J. Dongarra,et al.  Basic Linear Algebra Subprograms Technical (Blast) Forum Standard (1) , 2002, Int. J. High Perform. Comput. Appl..

[20]  H.-S.P. Wong,et al.  Extreme scaling with ultra-thin Si channel MOSFETs , 2002, Digest. International Electron Devices Meeting,.

[21]  M. Anantram,et al.  Two-dimensional quantum mechanical modeling of nanotransistors , 2001, cond-mat/0111290.

[22]  T. Boykin,et al.  Diagonal parameter shifts due to nearest-neighbor displacements in empirical tight-binding theory , 2002 .

[23]  James Demmel,et al.  SuperLU_DIST: A scalable distributed-memory sparse direct solver for unsymmetric linear systems , 2003, TOMS.

[24]  J. Appenzeller,et al.  Band-to-band tunneling in carbon nanotube field-effect transistors. , 2004, Physical review letters.

[25]  Timothy A. Davis,et al.  A column pre-ordering strategy for the unsymmetric-pattern multifrontal method , 2004, TOMS.

[26]  W. Fichtner,et al.  Atomistic simulation of nanowires in the sp3d5s* tight-binding formalism: From boundary conditions to strain calculations , 2006 .

[27]  Qin Zhang,et al.  Low-subthreshold-swing tunnel transistors , 2006, IEEE Electron Device Letters.

[28]  W. Fichtner,et al.  Three-Dimensional Full-Band Simulations of Si Nanowire Transistors , 2006, 2006 International Electron Devices Meeting.

[29]  Arvind Kumar,et al.  Silicon CMOS devices beyond scaling , 2006, IBM J. Res. Dev..

[30]  Donggun Park,et al.  Investigation of nanowire size dependency on TSNWFET , 2007, 2007 IEEE International Electron Devices Meeting.

[31]  T. Boykin,et al.  Multiband transmission calculations for nanowires using an optimized renormalization method , 2008 .

[32]  Andreas Schenk,et al.  A Parallel Sparse Linear Solver for Nearest-Neighbor Tight-Binding Problems , 2008, Euro-Par.

[33]  M. Luisier,et al.  Atomistic Simulation of Nanowire Transistors , 2008 .

[34]  M. Luisier,et al.  Full-band and atomistic simulation of n- and p-doped double-gate MOSFETs for the 22nm technology node , 2008, 2008 International Conference on Simulation of Semiconductor Processes and Devices.

[35]  Gerhard Klimeck,et al.  A multi-level parallel simulation approach to electron transport in nano-scale transistors , 2008, HiPC 2008.

[36]  Daehyun Kim,et al.  30-nm InAs Pseudomorphic HEMTs on an InP Substrate With a Current-Gain Cutoff Frequency of 628 GHz , 2008, IEEE Electron Device Letters.

[37]  H. Dai,et al.  Room-temperature all-semiconducting sub-10-nm graphene nanoribbon field-effect transistors. , 2008, Physical review letters.

[38]  M. Luisier,et al.  Performance analysis of statistical samples of graphene nanoribbon tunneling transistors with line edge roughness , 2009 .

[39]  M. Luisier,et al.  Atomistic full-band simulations of silicon nanowire transistors: Effects of electron-phonon scattering , 2009 .

[40]  M. Luisier,et al.  Performance analysis of ultra-scaled InAs HEMTs , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[41]  Eric Darve,et al.  A hybrid method for the parallel computation of Green's functions , 2009, J. Comput. Phys..

[42]  J. Jopling,et al.  High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[43]  Gerhard Klimeck,et al.  Numerical strategies towards peta-scale simulations of nanoelectronics devices , 2010, Parallel Comput..

[44]  Mathieu Luisier,et al.  A Parallel Implementation of Electron-Phonon Scattering in Nanoelectronic Devices up to 95k Cores , 2010, 2010 ACM/IEEE International Conference for High Performance Computing, Networking, Storage and Analysis.

[45]  S. Koester,et al.  Effect of Uniaxial Strain on the Drain Current of a Heterojunction Tunneling Field-Effect Transistor , 2011, IEEE Electron Device Letters.

[46]  W. Marsden.  I and J , 2012 .